Successive-approximation-register (SAR) analog-to-digital converters (ADCs) are frequently the architecture of choice for medium-to-high-resolution applications with medium to high sample rates. Resolutions for SAR ADCs most commonly range from 8 to 16 bits, and they provide low power consumption as well as a small form factor. This combination of features make these ADCs ideal for a wide variety of applications, such as portable/battery-powered instruments, pen digitizers, industrial controls, and data/signal acquisition. As the name implies, the SAR ADC basically implements a binary search algorithm. Therefore, while the internal circuitry may be running at several megahertz (MHz), the ADC sample rate is a fraction of that number due to the successive-approximation algorithm.
An attenuation capacitor (Ca) may be used between two capacitive DACs inside of a SAR ADC to reduce the range of capacitance values required. One side of the attenuation capacitor (Ca) is coupled to the most significant bit (msb) DAC (mDAC) and the other side of the attenuation capacitor (Ca) is coupled to a lower bit DAC (nDAC). The absolute value of the attenuation capacitor (Ca) depends on the values of the unit capacitors in the DACs ratio between the bottom plate parasitic of the unit capacitor and the top-plate parasitic capacitance of the lower bit DAC capacitors. It is critical to have the attenuation capacitor (Ca) capacitance manufactured to a tolerance of better than 0.25 percent accuracy with respect to the mDAC unit capacitor. Since the attenuation capacitor (Ca) depends on parasitic capacitance in an integrated circuit silicon die on which it is fabricated, this close accuracy has been achieved with prior technologies in two ways: (1) Silicon iteration based on measurement data to correct the parasitic capacitance value and then re-fabricate the silicon die of the SAR DAC (FIG. 1), and (2) use of a varactor (voltage variable capacitor) (FIG. 2), that introduces its own variable parasitic capacitance with respect to process and temperature variations.
Referring to FIG. 1, depicted is a schematic diagram of a typical prior technology split capacitive SAR DAC having an attenuation capacitor (CA) between an mDAC and an nDAC thereof. A problem exists for fine tuning of the attenuation capacitor (CA) of a SAR DAC using the silicon iteration based process prior technology method (1). The value of CA with no parasitic capacitance present is:
      C    A    =                    2        N                              2          N                -        α              ⁢          C      U      Where α is the ratio between unit capacitors of mDAC and nDAC. The value of CA with parasitic capacitance present is:
      C    A    =                              2          N                ⁢        λ                                          2            N                    ⁢          λ                -        α              ⁢          C      U      Where λ is a parasitic dependent factor. For example, a 5C-5C-2R implementation of the SAR DAC may have parasitic top-plate routing and a bottom plate of CA, wherein CA is approximately 107.204% of Cu, for Cu=150 femtofarads (fF) and CA=160.8 fF. A one percent (1%) error (1.6 fF) in CA results in about 0.3 DNL or about 3% error of 1 DNL. The total expected routing capacitor=60 fF. CA may be calculated from the parasitic capacitance, but it is impossible to get the correct capacitance needed the first time.
Referring to FIG. 2, depicted is a schematic diagram of a typical prior technology split capacitive DAC having an attenuation capacitor (Ca) between an mDAC and an nDAC thereof and a voltage variable capacitor compensation circuit. The prior technology method (2) using a fixed voltage reference (VREF), a compensation DAC (cDAC) 210 for controlling a voltage variable capacitor (varactor) 212 has a big capacitance variation across a range of process, voltage and temperature (PVT) conditions. The varactor is added to correct the parasitic variations of the attenuation capacitor (Ca) but adds much bigger capacitance variation by itself, e.g., the varactor adds parasitic capacitance to the top-plate of the nDAC. Use of the varactor 212 may result in performance variations and differential nonlinearity (DNL) sensitivity across a range PVT conditions.